RS Flipflop
Basically is Memory element which stores one bit of information.
The Name RS stands for R - Reset & S - Set
- It is constructed by feeding the outputs of two NOR gates back to the other NOR gates input.
- The inputs R and S are referred to as the Reset and Set inputs, respectively.
To understand the operation of the RS-flipflop (or RS-latch) consider the following scenarios:
When S = 0, R = 1; (Clock = 1)when the input are applied; when any one of the input is low NAND gate output is High. so the 1st flipflop output is High. The second flipflop out is Low Because Clock is high and R is high. Then one of input to the 4th gate is low so that the out is High. the Output of 4th Gate fed to the 3rd Gate i.e. both inputs are high so that Output of the Flipflop is LOW i.e RESET.
When S = 1, R = 0; (Clock = 1)
when input are applied as above mentioned, the 1st Gate inputs are High so that the output is Low. The 3rd Gate one of the input is Low (R=0) so the output is High. The 2nd Gate one of the input is low so the Output is High. the Out of 2nd Gate fed to the 4th Gate the Inputs of 4th Gate both are High. So that the Output is Low
when input are applied as above mentioned, the 1st Gate inputs are High so that the output is Low. The 3rd Gate one of the input is Low (R=0) so the output is High. The 2nd Gate one of the input is low so the Output is High. the Out of 2nd Gate fed to the 4th Gate the Inputs of 4th Gate both are High. So that the Output is Low
when input are applied as above mentioned, the 1st Gate inputs are High so that the output is Low. The 3rd Gate one of the input is Low (R=0) so the output is High. The 2nd Gate one of the input is low so the Output is High. the Out of 2nd Gate fed to the 4th Gate the Inputs of 4th Gate both are High. So that the Output is Low
When Clock = 0 (for any state of R & S)
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